EDN

Low-power 32M CMOS SRAM in a 12x20mm TSOP-I package

Alliance Memory has expanded its line of legacy low-power CMOS SRAMs with a new 32M IC (2M x 16 / 4M x 8 switchable), the company's highest density low-power device to date. Operating from a single ...
EDN

4M low-power CMOS SRAMs feature 55-ns access time from single 2.7V-3.6V supply

Alliance Memory has announced the AS6C4008A 4M (512K x 8) CMOS SRAM designed to operate from a single power supply of 2.7 V to 3.6 V and featuring a 55 ns access time. The new SRAM is optimized for ...
Yahoo Finance

Alliance Memory Launches New 8M Low-Power CMOS SRAM With 2.7-V to 3.6-V Power Supply in TSOP-I Package

SAN CARLOS, CA--(Marketwired - May 25, 2016) - Alliance Memory today expands its line of legacy low-power CMOS SRAMs with a new 8M IC (512K x 16 bit) in the 48-pin 12-mm by 20-mm TSOP-I package.
Electronics Weekly

EUV lithography makes first 22nm CMOS SRAM

Belgian research lab IMEC has revealed what it claims is the world’s first functional 22nm CMOS SRAM cells made using EUV lithography. “The 0.099µm 2 SRAM cells are made with FinFETs and have both the ...
Electronic Design

High-Density, Low-Power 32M CMOS SRAM

A line of legacy low-power CMOS SRAMs from Alliance Memory has been expanded with a new 32M IC (2M x 16 / 4M x 8 switchable), the company's highest density low-power device to date. Operating from a ...
Electronic Design

Crolles2 Alliance reveals ultra-dense SRAM cell in 45 nm conventional bulk CMOS

The Crolles2 Alliance, which includes Freescale Semiconductor, Philips and STMicroelectronics, has created six-transistor SRAM-bit cells with an area of less than 0.25 square microns, or about half ...
Semiconductor Engineering

Zeno Semi Expands On-Chip Memory

San Jose, Calif.-based startup Zeno Semiconductor is testing modifications and a smaller process node for the single-transistor 28nm SRAM chip it introduced in 2016, which could boost space for ...
Semiconductor Engineering

SRAM-Based IMC For Cryogenic CMOS Using Commercial 5 nm FinFETs

A technical paper titled “Cryogenic In-Memory Computing for Quantum Processors Using Commercial 5-nm FinFETs” was published by researchers at University of Stuttgart, Indian Institute of Technology ...
Science Daily

Non-volatile bistable memory circuits for highly energy-efficient CMOS logic systems

Non-volatile bistable memory circuits pave the way for highly energy-efficient CMOS logic systems. Non-volatile bistable memory circuits being developed by Satoshi Sugahara and his team at Tokyo Tech ...
EurekAlert!

Demonstration of high-speed SOT-MRAM memory cell compatible with 300mm Si CMOS technology

Researchers at Tohoku University have announced the demonstration of high-speed spin-orbit-torque (SOT) magnetoresistive random access memory cell compatible with 300 mm Si CMOS technology. The demand ...