EDN

Static verification needs a parallel approach

Next generation communications and consumer electronics products, especiallythose based on 90-nanometer technology and below, will include chips thatexceed 70 million gates. We providers of EDA tools ...
Semiconductor Engineering

Power-Aware Intent And Structural Verification Of Low-Power Designs

Cell-level and pin-level attributes from Liberty are mandatorily required for accurate PA-Static verification at the GL-netlist (post-synthesis) and PG-netlist (post P&R) levels of the design.
Business Wire

Aldec Provides Static Verification for RISC-V Designs with the Latest Release of ALINT-PRO

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has added a RISC-V focused static verification ...
EDN

SOC DFT verification with static analysis

To achieve higher quality on multi­million gate designs and high-speed ASICs, manufacturers are relying on structured DFT (design-for-test) methodologies such as scan, at-speed test, scan compression, ...
Semiconductor Engineering

Information Flow Verification Framework Integrating Static and Formal Verification Methods At The Pre-Silicon Stage (U. of Florida)

“Modern system-on-chips (SoCs) are becoming prone to numerous security vulnerabilities due to their ever-growing complexity and size. Therefore, a comprehensive security verification framework is ...
Embedded

Next-generation of SPARK static verification toolset released

Altran and AdaCore have released an enhanced upgrade to their integrated development and verification environment for the ADA-based SPARK language, Version 14.0. According to Keith Williams, Group ...
Nasdaq

Synopsys VC LP for Low Power Signoff Verification Delivers Up to 5X Runtime Gain at Samsung

MOUNTAIN VIEW, Calif., Nov. 7, 2019 /PRNewswire/ -- Synopsys, Inc. (Nasdaq: SNPS) today announced that Samsung, a global leader in enterprise mobility and information technology, has adopted the ...